View DS25LV02_8710766.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 17 051106 general description the DS25LV02 provides data storage and serial number identification for battery packs. the low- voltage dallas 1-wire interface enables serial communication on a single battery contact and the 64-bit unique serial number allows multidrop networking and identification of individual devices. the 1024-bit eprom memory is organized as 4 pages of 32 bytes each and supports storage of battery cell characteristics, charging voltage, current and temperature parameters, as well as battery pack manufacturing data. crc verification provides data integrity during communication. the eprom pages are in-circuit writable and can be individually locked to protect data. the DS25LV02 is designed to be completely backward-compatible with the ds2502 for existing designs. applications cell phones/smartphones digital cameras mp3 players typical application circuit features 128 bytes of eprom storage organized into four separately lockable pages backward-compatible with ds2502 dallas 1-wire interface input logic thresholds compatible with 1.8v i/o supply rail unique 64-bit serial number operates with v dd as low as 2.2v tiny, thin sot-23 package pin configuration top view 5-pin thin-sot (tsot) ordering information part temp range pin-package DS25LV02r+u -30c to +85c 5 thin sot DS25LV02r+t& r -30c to +85c 5 thin sot in tape-and-reel +denotes lead-free package. 1-wire is a registered trademark of dallas semiconductor. certain commands, modes, and registers are capitalized for clarity. DS25LV02 low-voltage 1024-bit eprom www.maxim-ic.com downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 2 of 17 absolute maximum ratings voltage range on dq, relative to v ss -0.3v to +12v voltage range on v dd , relative to v ss -0.3v to +6v operating temperature range -30c to +85c storage temperature range -55c to +125c soldering temperature see ipc/jedec j-std-020a specification stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stres s rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operat ional sections of t he specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affe ct device. recommended dc operating conditions (2.2v v dd 5.5v, t a = -30c to +85c.) parameter symbol conditions min typ max units supply voltage v dd (notes 1, 2) 2.2 5.5 v data pin communication voltage v dq (note 1) -0.3 +5.5 v data pin programming voltage v pp (notes 1, 2, 5) 11.5 12.0 v dc electrical characteristics (2.2v v dd 5.5v, t a = -30c to +85c.) parameter symbol conditions min typ max units i dd0 dq idle (note 4) 0.8 2 supply current i dd1 communication mode, dq active 300 a input-logic high: dq v ih (note 1) 1.5 v v dd 2.5v 0.6 input-logic low: dq (note 1) v il 0.4 v output-logic low: dq v ol i ol = 4ma (note 1) 0.4 v pulldown current: dq i pd 0.5 a eprom reliability specification (2.2v v dd 5.5v, t a = -30 c to +85 c.) parameter symbol conditions min typ max units storage t ees (notes 2, 3) 10 years downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 3 of 17 ac electrical characteristics: eprom programming (3.0v v dd 5.5v, t a = -30c to +50c.) parameter symbol conditions min typ max units programming pulse width t pp (notes 1, 2, 5, 6) 480 5000 s program voltage rise time t rp (notes 1, 2, 5) 0.5 5.0 s program voltage fall time t fp (notes 1, 2, 5) 0.5 5.0 s programming current: dq pin i pp (notes 2, 5, 7) 6 10 ma ac electrical characteristics: 1-wire interface (2.2v v dd 5.5v, t a = -30 c to +85 c.) parameter symbol conditions min typ max units time slot t slot 60 120 s recovery time t rec 1 s write-0 low time t low0 60 120 s write-1 low time t low1 1 15 s read-data valid t rdv 15 s reset-time high t rsth 480 s reset-time low t rstl 480 960 s presence-detect high t pdh 15 60 s presence-detect low t pdl 60 240 s delay to program pulse t dp 5 s delay to verify t dv 5 s dq capacitance c dq 50 pf note 1: all voltages are referenced to v ss . note 2: programming of the eprom data and eprom status fields require a limited temperature range of 0 c to 50 c and limited v dd voltage range of 3.0v to 5.5v. note 3: storage for t ees at +50 c. note 4: dq < v il for t > 1.5ms or dq > v ih for t > 1.5ms [1-wire oscillator shut down]. note 5: programming pulse on dq pin must be shaped to conform with rise, fall, and width timing spe cifications. see figure 7. eprom programming diagram). note 6: the accumulative duration of all programming pulses for each address must not exceed 5ms. note 7: specification is guaranteed by design. downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 4 of 17 pin description pin name function 1, 3 n.c. no connection 2 v ss supply gnd and reference for serial communication. attach v ss to battery-pack negative terminal. 4 v dd supply input. bypass to v ss with 0.01 f (typ). 5 dq serial interface data i/o pin. bidirectional data transmit and receive at 16kbps. input for programming voltage pulse during eprom programming. internal 0.5 a pulldown ensures idle mode is entered when no dq pullup is present. figure 1. block diagram dq vss hv shaper 1-wire i/f and control eprom array reg. vdd_int vdd dout din vpp hv detect hv 0.5 a detailed description the DS25LV02 provides battery-pack identification and data storage. a 128-byte eprom memory array and an 8 byte status field accessed by a low-voltage 1-wire interface. each DS25LV02 has a uniqu e 64-bit net address (rom id) for identification. the eprom is divided into four 32-byte pages. an additional 8-byte status field provides lock bit and page redirection information to the user. eprom writing occurs one byte at a time by supplying a 12v pu lse on the dq line in-between each byte written. each page can be individually locked by clearing the appropriate bit in the stat us field. data is read sequentially from a starting address through the end of the array. crc verification provides integrity of all read and written data. functional compatibility has been maintained between the ds2502 and DS25LV02 at the net address/rom command and function command levels for reading and writing the memory data and status data fields. downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 5 of 17 eprom memory data field the DS25LV02 has a linear address space for access to the eprom data field. the eprom data field is organized as 4 pages of 32 bytes each as shown in table 1. the read memory and read data/generate crc memory function commands provide read access to the 1024 bits of the eprom data field. the write memory function command provides write access to the eprom data field. when received from the factory, th e entire 1024-bit eprom data field is erased and returns logical 1s when read. bits within the data field are one time programmable. programming changes the bit value to logical zero from the factory default erased valu e of a logical 1. once a bit is programmed, it cannot be set back to a logical 1. table 1. eprom data field address (hex) description read/write 0000C001f page 0 (32 bytes) r/w* 0020C003f page 1 (32 bytes) r/w* 0040C005f page 2 (32 bytes) r/w* 0060C007f page 3 (32 bytes) r/w* 0080Cffff reserved * one-time write to 0 for each bit. read memory [f0h] the read memory command is used to read data from page 0 to page 3 of the 1024-bit eprom data field. the bus master follows the command byte with a 2-byte address (ta1 = (t7:t0), ta2 = (t15:t8)) that indi cates a starting byte location within the data field. an 8-bit crc of the command byte and address bytes is computed by the DS25LV02 and read back by the bus master to confirm that the correct command word and starting address were received. if the crc is deemed to be incorrect by the bus master, the bus master should issue a r eset pulse and repeat the entire sequence. if the crc is deemed to be correct by the bus master, read time slots can be issued to receive data from the eprom data field starting at the initial address. the bus master can iss ue a reset pulse at any point or continue to issue read time slots until the end of page 3 of the data field is reached. if reading continues through the end of page 3, the bus master can issue eight additional read time slots and the DS25LV02 will respond with a 8-bit crc of all data bytes read from the initial starting byte through the last byte of page 3. terminating the command transaction with a reset pulse prior to reaching the end of page 3 results in a loss of availability of the 8-bit crc. read data/generate 8-bit crc [c3h] the read data/generate 8-bit crc command is used to read data from page 0 to page 3 of the 1024-bit eprom data field. the bus master follows the command byte with a 2-byte address (ta1 = (t7:t0), ta2 = (t15:t8)) that indicates a starting byte location within the data field. an 8-bit crc of the command byte and address bytes is computed by the DS25LV02 and read back by the bus master to c onfirm that the correct command word and starting address were received. if the crc is deemed to be incorrect by the bus master, the bus master should issue a reset pulse and repeat the entire sequence. if the crc is deemed to be correct by the bus master, read time slots can be issued to receive data from the eprom data field starting at the initial address. the bus master can issue a reset pulse at any point or continue to issue read time slots until the end of the 32-byte page is reached. if reading occurs through the end of the 32-byte page, the bus master can issue eight additional read time slots and the DS25LV02 will respond with an 8-bit crc of all data bytes read from the initial starting byte through the last byte of the current page. after the crc is received, additional read time slots return data starting with the first byte of the next page. this sequence will continue until the bus master reads page 3 and its accompanying crc. thus each page of data can be considered to be 33 bytes long: the 32 bytes of user-programmed eprom data and an 8-bit crc that gets generated automatically at the end of each page. the read data/generate 8-bit crc command sequence can be exited at any point by issuing a reset pulse. downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 6 of 17 write memory [0fh] the write memory command is used to program the 1024-bit eprom data field. programming is performed one or more bytes at a time, with crcs of the master-to-slave bit stream provided for data integrity. to begin a memory write, the bus master issues the write memory function command followed by a 2-byte address argument (ta1 = (t7:t0), ta2 = (t15:t8)) and a 1-byte data argument (d7:d0). the 2-byte address argument sets the starting byte position in the eprom data field of the first byte to be written. the data argument provides data for the first byte to be written. the master must issue 8 read timeslots following the data argument. an 8-bit crc of the command byte, address bytes and data byte computed by the DS25LV02 is returned in the 8 timeslots to enable the master to check the integrity of the communication. if the crc is deemed to be incorrect by the bus master, the bus master should issue a reset pulse and repeat the entire sequence. if the crc is deemed to be correct by the bus master, a programming pulse can be issued to program the byte position within the eprom data field pointed to by t15:t0. following the programming pulse, the bus master must issue 8 read timeslots. the read timeslots return the eprom data byte value (least significant bit first) for confirm ation by the master. the bus master can issue a reset pulse at any point after issuing the program pulse to end the write operation , or continue the write operation with the next byte in the eprom data field. if a the write operation is continued, the DS25LV02 automatically increments the internal address pointer to select the next byte in the eprom data fi eld, and the new value of t7:t0 is loaded into the 8-bit crc generator as the starting value. the bus master issues the next 1-byte data argument followed by 8 read timeslots to return the crc computed by the DS25LV02. the value returned is computed with d7:d0, using t7:t0 as the starting value. if the crc is deemed to be incorrect by the bus master, the bus master should issue a reset pulse and repeat the entire sequence. if the crc is deemed to be correct by the bus master, a programming pulse can be issued to program the byte position pointed to by t15:t0 . following the programming pulse, the bus master must issue 8 read timeslots. the read timeslots return the eprom data byte value (least significant bit first) for confirmation by the master. the write operation can be continued until the end of the eprom data field is reached by repeating the sequence of issuing a 1-byte data argument, 8 read timeslots to return crc, a programming pulse, and 8 read timeslots to return eprom data. eprom status the DS25LV02 has a separate 8-byte linear address space for access to the eprom status data field using the read status and write status function commands. read status [aah] the read status command is used to read data from the eprom status data field. the bus master follows t he command byte with a 2-byte address (ta1 = (t7:t0), ta2 = (t15:t8)) that indicates a starting byte location within the data field. an 8-bit crc of the command byte and address bytes is computed by the DS25LV02 and read back by the bus master to confirm that the correct command word and starting address were received. if the crc is deemed to be incorrect by the bus master, a reset pulse should be issued and the entire sequence repeated. if the crc is deemed to be correct by the bus master, read timeslots can be issued to receive data starting at the initial address. the bus master can issue a reset pulse at any point or continue to issue read timeslots until the end of the eprom status data field is reached. if reading occurs through the end of the eprom status data field, the bu s master can issue 8 additional read timeslots and the ds25lv 02 will respond with a 8-bit crc of all data bytes read from the initial starting byte through the last byte. additional read timeslots return logical 1s until the internal address reaches a multiple of 128. then data is returned from address 0000h. the read status command sequence can be ended at any point by issuing a reset pulse. write status [55h] the write status command is used to program the eprom status field. to begin a status field write, the bus master issues the write status function command followed by a 2-byte address argument (ta1 = (t7:t0), ta2 = (t15:t8)) and a 1-byte data argument (d7:d0). the 2-byte address argument sets the starting byte position in the eprom status field of the first byte to be written. the data argument provides data for the first byte to be written. the master must issue 8 read timeslots following the data argument. an 8-bit crc of the command byte, address bytes, and data byte computed by the DS25LV02 is returned in the 8 timeslots to enable the master to check the integrity of the communication. if the crc is deemed to be incorrect by the bus master, the bus master should issue a reset pulse and repeat the entire sequence. if the crc is deemed to downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 7 of 17 be correct by the bus master, a programming pulse can be issued to program the byte position within the eprom status field pointed to by t15:t0. following the programming pulse, the bus master must issue 8 read timeslots. the read timeslots return the eprom status byte value (least significant bit first) for confirmation by the master. the bus master can issue a reset pulse at any point after issuing the program pulse to end the write operation , or continue the write operation with the next byte in the eprom status field. if the write operation is continued, the DS25LV02 automatically increments the internal address pointer to select the next byte in the eprom st atus field, and the new value of t7:t0 is loaded into the 8-bit crc generator as the starting value. the bus master issues the next 1-byte data argument followed by 8 read timeslots to return the crc computed by the DS25LV02. the value returned is computed with d7:d0, using t7:t0 as the starting value. if the crc is deemed to be incorrect by the bus master, the bus master should issue a reset pulse and repeat the entire sequence. if the crc is deemed to be correct by the bus master, a programming pulse can be issued to program the byte position pointed to by t15:t0 . following the programming pulse, the bus master must issue 8 read timeslots. the read timeslots return the eprom status byte value (least significant bit first) for confirmation by the master. the write operation can be continued until the end of the eprom status field is reached by repeating the sequence of issuing a 1-byte data argument, 8 read timeslots to return crc, a programming pulse, and 8 read timeslots to return eprom byte value. table 2. eprom status field address (hex) description read/write 0000 write protect page bits b0: page 0 write protect b1: page 1 write protect b2: page 2 write protect b3: page 3 write protect b4: reserved for tmex b5: reserved for tmex b6: reserved for tmex b7: reserved for tmex r/w* 0001 page redirection byte for page 0 r/w* 0002 page redirection byte for page 1 r/w* 0003 page redirection byte for page 2 r/w* 0004 page redirection byte for page 3 r/w* 0005-0006 reserved r 0007 factory programmed to 00h r * one-time write to 0 for each bit. downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 8 of 17 table 3. eprom memory a nd status function commands command hex function read memory f0 read data from the lower 1024 bits of the 1024-bit eprom memory data field. generates a crc value if a read continues through the end of the last page. read data/generate crc c3 read data from the lower 1024 bits of the 1024-bit eprom memory data field. generates a crc value of the data if read continues through the end of the page. write memory 0f write data to the eprom data field. read status aa read data from the 8-byte eprom status field. generates a crc if read continues through the end of the field. write status 55 write the page protection bits and page redirection bytes in the eprom status field. note : the write memory, read memory, read data/generate crc, write status, and read status commands filter the target address (ta2:ta1) value with a 007fh and mask that limits the addressable size of the eprom data field and eprom status field to 1024 bits. target address values equal to or greater than 0080h (128 decimal) return data from the lower 128 bytes of the respective data field. the result of the filtering is that the internal address wraps around every 128 bytes as the external target address increments in multiples of 128. for instance, each time a read operation crosses a 128-byte boundary (0080h, 0100h, ff00h, ff80h) data retrieval b egins again at address 0000h. this process repeats until reading occurs through the end of the 64kb memory space addressable by t15:t0. it is also important to note that the filter is applied prior to calculation of the crc, so that target address values that are multiples of 128 return the same crc. the crc values should be considered correct only for t15:t0 in the range of 0000h to 007fh. 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. a multidrop bus is a 1-wire bus with multiple slaves, while a single-drop bus has only one slave device. in all instances, the ds 25lv02 is a slave device. the bus master is typically a microprocessor in the host system. the discussion of this bus system consists of five topics: 64-bit net address, crc generation, hardw are configuration, transaction sequence, and 1-wire signaling. 64-bit net address (rom id) each DS25LV02 has a unique, factory-programmed 1-wire net address that is 64 bits in length. the term net address is synonymous with the rom id or rom code terms used in the ds2502 and older dallas 1-wire documentation. the first 8 bits of the net address are the 1-wire family code (09h for the standard ds25l v02). the next 48 bits are a unique serial number. the last 8 bits are a cyclic redundancy check (crc) of the first 56 bits (see figure 2). the 64-bit net address and the 1-wire i/o circuitry built into the device enable the DS25LV02 to communicate through the 1-wire protocol detailed in this data sheet. figure 2. 1-wire net address format 8-bit crc 48-bit serial number 8-bit family code (09h) msb lsb downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 9 of 17 crc generation the DS25LV02 has an 8-bit crc stored in the most significant byte of its 1-wire net address and generates a crc during some command protocols. to ensure error-free transmission of the address, the host sy stem can compute a crc value from the first 56 bits of the address and compare it to the crc from the DS25LV02. the host system is responsible for verifying the crc value and taking action as a result. the DS25LV02 does not compare crc values and does not prevent a command sequence from proceeding as a result of a crc mismatch. proper use of the crc can result in a communicati on channel with a very high level of integrity. the crc can be generated by the host using a circuit consis ting of a shift register and xor gates as shown in figure 3, or it can be generated in software using the polynomial x 8 + x 5 + x 4 + 1. additional information about the dallas 1-wire crc is available in application note 27: understanding and using cyclic redundancy checks with dallas semiconductor i button products ( www.maxim-ic.com/appnoteindex ). in the circuit in figure 3, the shift register bits are initialized to 0. then, starting with the least s ignificant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. figure 3. 1-wire crc generation block diagram during some command sequences, the DS25LV02 also generates an 8-bit crc and provides this value to the bus master to facilitate validation for the transfer of command, address, and data from the bus master to the DS25LV02. the DS25LV02 computes an 8-bit crc for the command and address bytes received from the bus master for the read memory, read status and read/generate crc commands to confirm that these bytes have been received correctly. the crc generator on the DS25LV02 is also used to provide verification of error-free data transfer as each eprom page is sent to the master during a read data/generate crc command and for the 8 bytes of information in the status memory field. in each case where a crc is used for data transfer validation, the bus master must calculate the crc value usin g the same polynomial function and compare the calculated value to the crc either stored in the DS25LV02 net address or computed by the DS25LV02. the comparison of crc values and decision to continue with an operation are determined entirely by the bus master. there is no circuitry in the DS25LV02 that prevents the command sequence from proceeding if the stored or calculated crc from the DS25LV02 and the calculated crc from the host do not match. hardware configuration because the 1-wire bus has only a single line, it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must connect to the bus with open-drain or tri-state output drivers. the DS25LV02 uses an open-drain output driver as part of the bidirectional interface circuitry shown in figure 4. if a bidirectional pin is not available on the bus master, separat e output and input pins can be connected together. the 1-wire bus must have a pullup resistor at the bus-master end of the bus. a value between 2k and 5k is recommended. the idle state for the 1-wire bus is high. if, for any reason, a bus transaction must be suspended, the bus must be left in the idle state to properly resume the transaction later. note that if the bus is left low fo r more msb xor xor lsb xor input i button is a registered trademark of dallas semiconductor. downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 10 of 17 than t low0 , slave devices on the bus begin to interpret the low period as a reset pulse, effectively terminating the transaction. figure 4. 1-wire bus interface circuitry vpullup (1.8 to 5.5v) rxtx rx rx = receive tx = transmit ~100 ohm mosfet bus master device 1-wire port (dq) 4.7k tx ~0.5 a transaction sequence the protocol for accessing the DS25LV02 through the 1-wire port is as follows: initialization net address command function command(s) data transfer all transactions of the 1-wire bus begin with an initialization sequence consisting of a reset pulse transmitted b y the bus master, followed by a presence pulse simultaneously transmitted by the DS25LV02 and any other slaves on the bus. the presence pulse tells the bus master that one or more devices are on the bus and ready to operate. for more details, see below. net address commands once the bus master has detected the presence of one or more slaves, it can issue one of the net address commands described in the following paragraphs. the name of each net address command (rom command) is followed by the 8-bit opcode for that command in square brackets. read net address [33h]. this command allows the bus master to read the DS25LV02s 1-wire net address. the bus master follows the read net address command with 64 read timeslots allowing the 1-wire slave to transmit its address. this command can only be used if there is a single slave on the bus. if more than one slave is present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-and res ult). match net address [55h]. this command allows the bus master to specifically address one DS25LV02 on the 1-wire bus. following this command, the bus master transmits the 64 bit net address of the desired s lave device. only the addressed DS25LV02 responds to any subsequent function command. all other slave devices ignor e the function command and wait for a reset pulse. this command can be used with one or more slave devices on the bus. skip net address [cch]. this command saves time when there is only one DS25LV02 on the bus by allowing the bus master to issue a function command without specifying the address of the slave. if more than one slave device is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at the same time. search net address [f0h]. this command allows the bus master to use a process of elimination to identify the 1-wire net addresses of all slave devices on the bus. the search process involves the repetition of a simple three- downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 11 of 17 step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple three-step routine on each bit location of the net address. after one complete pass through all 64 bits, the bus master knows the address of one device. the remaining devices can then be identified on additional iterations of the process. refer to chapter 5 of the book of ds19xx i button standards for a comprehensive discussion of a net address search, including an actual example ( www.maxim-ic.com/ibuttonbook ). i/o signaling the 1-wire bus requires strict signaling protocols to ensure data integrity. the four protocols used by the DS25LV02 are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data. the bus master initiates all these types of signaling except the presence pulse. the initialization sequence required to begin any communication with the DS25LV02 is shown in figur e 5. a presence pulse following a reset pulse indicates that the DS25LV02 is ready to accept a net addres s command. the bus master transmits (tx) a reset pulse for t rstl . the bus master then releases the line and goes into receive mode (rx). the 1-wire bus line is then pulled high by the pullup resistor. after detecting the r ising edge on the dq pin, the DS25LV02 waits for t pdh and then transmits the presence pulse for t pdl . figure 5. 1-wire initialization sequence write-time slots a write-time slot is initiated when the bus master pulls the 1-wire bus from a logic-high (inactive) level to a logic-low level. there are two types of write-time slots: write 1 and write 0. all write-time slots must be t slot in duration with a 1 s minimum recovery time, t rec , between cycles. the DS25LV02 samples the 1-wire bus line between t low1_max and t low0_min after the line falls. if the line is high when sampled, a write 1 occurs. if the line is low when sampled, a write 0 occurs. the sample window is illustrated in figure 6. for the bus master to generate a write-1 time slot, the bus line must be pulled low and then released, allowing the line to be pulled high less than t rdv after the start of the write time slot. for the host to generate a write-0 time slot, the bus line must be pulled low and held low for the duration of the write-time slot. read-time slots a read-time slot is initiated when the bus master pulls the 1-wire bus line from a logic-high level to a logic-lo w level. the bus master must keep the bus line low for at least 1 s and then release it to allow the DS25LV02 to present valid data. the bus master can then sample the data t rdv from the start of the read-time slot. by the end of the read-time slot, the DS25LV02 releases the bus line and allows it to be pulled high by the external pul lup resistor. all read-time slots must be t slot in duration with a 1 s minimum recovery time, t rec , between cycles. see figure 6 and the timing specifications in the electrical characteristics table for more information. t r s tl t pdl t r s th t pdh pack+ pack- line type legend: bus master active lo w slave active l ow resistor pullup both bus master and slave active low dq downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 12 of 17 figure 6. 1-wire write and read time slots write 0 slot write 1 slot t slot t low0 t slot t rec t low1 v pullup gnd device sample window min typ max 15 s 2 s 15 s 30 s 1 s 3 s device sample window min typ max 15 s 2 s 15 s 30 s 1 s 3 s overdrive standard mode >1 s read data slot data = 0 t slot 15 s t slot t rec v pullup gnd master sample window t rdv 15 s master sample window >1 s data = 1 overdrive standard mode 2 s 2 s line type legend: bus master active low slave device active low both bus master and slave device resistor pullup active low t rdv downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 13 of 17 figure 7. eprom programming diagram skip rom command write memory command 1-wire reset presence pulse programming pulse t rp t fp t pp ta1, ta2, data and crc bytes t dp vpp min = 11.5v, vpp max = 12.0v verification read t dv package information (for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 14 of 17 figure 8. operational flow chart yes no yes yes yes yes no master tx net address command DS25LV02 tx presence pulse 33h/39h read 55h match f0h search cch skip master tx reset pulse no no no DS25LV02 tx family code 1 byte DS25LV02 tx serial number 6 bytes DS25LV02 tx crc 1 byte yes master tx bit 0 yes bit 0 match? master tx bit 1 no yes bit 1 match? DS25LV02 tx bit 1 master tx bit 1 bit 0 match? master tx bit 63 bit 63 match? DS25LV02 tx bit 1 DS25LV02 tx bit 63 master tx bit 63 DS25LV02 tx bit 63 DS25LV02 tx bit 0 master tx bit 0 DS25LV02 tx bit 0 bit 1 match? no no no start go to start go to memory commands 1 go to memory commands 1 downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 15 of 17 figure 8. operational flow chart (continued) no yes yes yes master tx memory function command f0h read memory ? aah read status ? no crc correct ? no no memory commands 1 go to start bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) bus master rx 8-bit crc of command and address bus master rx data from data memory bus master tx reset ? end of data memory ? bus master tx reset ? bus master tx reset ? bus master rx 8-bit crc of data bus master rx all 1's yes no yes no DS25LV02 increments address counter yes no bus master tx reset DS25LV02 tx presence pulse yes yes yes crc correct ? no no bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) bus master rx 8-bit crc of command and address bus master rx data from status memory bus master tx reset ? end of page ? bus master tx reset ? bus master tx reset ? bus master rx 8-bit crc of status data bus master rx all 1's yes no yes no DS25LV02 i ncrements address counter yes no go to memory commands 2 downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 16 of 17 figure 8. operational flow chart (continued) c3h read data & generate crc ? no memory commands 2 go to start bus master tx reset DS25LV02 tx presence pulse yes yes yes crc correct ? no no bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) bus master rx 8-bit crc of command and address bus master rx data from data memory bus master tx reset ? end of page ? bus master tx reset ? bus master rx 8-bit crc of status data bus master rx all 1's yes no yes no DS25LV02 increments address counter yes no go to memory commands 3 bus master tx reset crc correct ? end of memory ? yes no downloaded from: http:///
DS25LV02: low-voltage 1024-bit eprom 17 of 17 figure 8. operational flow chart (continued) no yes yes 0fh write memory ? no no memory commands 3 bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) bus master tx data byte (d7:d0) bus master rx 8-bit crc of command, address, and data (1 st pass ) crc of address and data (subsequent passes) crc correct ? eprom byte = correct ? end of data memory ? DS25LV02 increments address counter DS25LV02 loads lsb of new address into crc generator yes no bus master tx reset yes no bus master tx program pulse DS25LV02 copies scratchpad to data eprom bus master rx byte from eprom no yes yes 55h write status ? no no go to start bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) bus master tx data byte (d7:d0) bus master rx crc16 of command, address, and data (1 st pass) crc16 of address and data (subsequent passes) crc correct ? eprom byte = correct ? end of status memory ? DS25LV02 increments address counter DS25LV02 loads lsb of new address into crc generator yes no yes no DS25LV02 tx presence pulse bus master tx program pulse DS25LV02 copies scratchpad to status eprom bus master rx byte from eprom bus master tx reset bus master tx reset downloaded from: http:///

▲Up To Search▲

Price & Availability of DS25LV02

	To Download DS25LV02 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .